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stk11c68-5 (s md5962-92324) 64 kbit (8 k x 8) softstore nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-51001 rev. *c revised february 16, 2012 features 35 ns, 45 ns, and 55 ns access times pin compatible with industry standard srams software initiated nonvolatile store unlimited read and write endurance automatic recall to sram on power-up unlimited recall cycles 1,000,000 store cycles 100 year data retention single 5 v 10% operation military temperature 28-pin (300 mil) cdip and 28-pad lcc packages functional description the cypress stk11c68-5 is a 64 kb fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorpor ate quantumtrap technology to produce the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable quantumtrap cell. data transfers under software control from sram to the nonvolatile elements (the store operation). on power-up, data is automatically restored to the sram (the recall operation) from the nonvolatile memory. recall operations are also available under software control. store/ recall control power control software detect static ram array 128 x 512 quantum trap 128 x 512 store recall column i/o column dec row decoder input buffers oe ce we hsb v cc v cap a 0 - a 12 a 0 a 1 a 2 a 3 a 4 a 10 a 5 a 6 a 7 a 8 a 9 a 11 a 12 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 logic block diagram
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 2 of 17 pinouts pin definitions pin name alt i/o type description a 0 ?a 12 input address inputs . used to select one of the 8,192 bytes of the nvsram. dq 0 -dq 7 input/output bidirectional data i/o lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce e input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. v ss ground ground for the device . the device is connect ed to ground of the system. v cc power supply power supply inputs to the device . nc a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v cc nc a 8 a 9 a 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 10 dq 7 dq 6 dq 5 dq 4 dq 3 a 12 we oe ce (top) figure 1. pin diagram - 28-pin dip figure 2. pin diagram - 28-pin llc
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 3 of 17 contents device operation .............................................................. 4 sram read ....................................................................... 4 sram write ....................................................................... 4 software store ............................................................... 4 software recall ............................................................. 4 hardware recall (power up) ........................................ 4 hardware protect .............................................................. 4 noise considerations ....................................................... 4 low average active power .............................................. 5 best practices ................................................................... 5 maximum ratings ............................................................. 6 operating range .............................................................. 6 dc electrical characteristics .......................................... 6 data retention and endurance ....................................... 6 capacitance ...................................................................... 6 thermal resistance .......................................................... 7 ac test conditions .......................................................... 7 sram read cycle ...................................................... 8 sram write cycle ....................................................... 9 autostore inhibit or power up recall .................... 10 software controlled store/recall cycle ................ 11 part numbering nomenclature ...................................... 12 ordering information ...................................................... 13 acronyms ........................................................................ 16 document conventions ................................................. 16 units of measure ....................................................... 16 document history page ................................................ 17 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 4 of 17 device operation the stk11c68-5 (smd5962-92324) is a versatile memory chip that provides several modes of operation. the stk11c68-5 (smd5962-92324) can operate as a standard 8k x 8 sram. it has an 8k x 8 nonvolatile elements shadow to which the sram information can be copied or from which the sram can be updated in nonvolatile mode. sram read the stk11c68-5 (smd5962-92324) performs a read cycle whenever ce and oe are low while we is high. the address specified on pins a 0?12 determines the 8,192 data bytes accessed. when the read is in itiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins. they remain valid until another address change or until ce or oe is brought high, or we is brought low. sram write a write cycle is performed whenever ce and we are low. the address inputs must be stabl e before entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common i/o pins dq 0?7 are written into the memory if it has valid t sd . this is done before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. software store data is transferred from the sram to the nonvolatile memory by a software address sequence. the stk11c68-5 (smd5962-92324) software store cycle is initiated by executing sequential ce controlled read cycles from six specific address locations in exact order. during the store cycle, an erase of the previous nonvolatil e data is first performed followed by a program of the nonvolatile elements. when a store cycle is initiated, input and output are disabl ed until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence. if they intervene, the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence is performed: 1. read address 0x0000, valid read 2. read address 0x1555, valid read 3. read address 0x0aaa, valid read 4. read address 0x1fff, valid read 5. read address 0x10f0, valid read 6. read address 0x0f0f, initiate store cycle the software sequence is clocked with ce controlled reads. when the sixth address in the sequence is entered, the store cycle commences and the chip is di sabled. it is important that read cycles and not write cycles are used in the sequence. it is not necessary that oe is low for a valid sequence. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations is performed: 1. read address 0x0000, valid read 2. read address 0x1555, valid read 3. read address 0x0aaa, valid read 4. read address 0x1fff, valid read 5. read address 0x10f0, valid read 6. read address 0x0f0e, initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared; then, the nonvolatile information is transferred into the sram cells. after the t recall cycle time, the sram is again ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. the nonvolatile data can be recalled for an unlimited number of times. hardware recall (power up) during power up or after any low-power condition (v cc < v reset ), an internal recall request is latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. if the stk11c68-5 (smd5962-92324) is in a write state at the end of power-up recall, the sram data is corrupted. to help avoid this situation, a 10 k ? resistor is connected either between we and system v cc or between ce and system v cc . hardware protect the stk11c68-5 (smd5962-92324) offers hardware protection against inadvertent store operation and sram writes during low voltage conditions. when v cap < v switch , all externally initiated store operations and sram writes are inhibited. noise considerations the stk11c68-5 (smd5962-92324) is a high-speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high-speed cmos ics, careful routing of power, ground, and signals reduce circuit noise.
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 5 of 17 low average active power cmos technology provides the stk11c68-5 (smd5962-92324) the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. figure 3 and figure 4 shows the relationship between i cc and read or write cycle time. worst case current consumption is shown for both cmos and ttl input levels (commercial temperature range, v cc = 5.5 v, 100% duty cycle on chip enable). only standby current is drawn when the chip is disabled. the overall average current drawn by the stk11c68-5 (smd5962-92324) depends on the following items: duty cycle of chip enable overall cycle rate for accesses ratio of reads to writes cmos versus ttl input levels operating temperature v cc level i/o loading best practices cypress nvsram products have been used effectively for over 15 years. while ease of use is one of the product?s main system values, the experience gained from working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites sometimes reprograms th ese values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. the end product?s firmware must not assume that an nv array is in a set programmed state. routines that check memory content values to determine fi rst time system configuration. cold or warm boot status, and so on must always program a unique nv pattern (for example, complex 4-byte pattern of 46 e6 49 53 hex or more random by tes) as part of the final system manufacturing test. this is to ensure these system routines work consistently. figure 3. current versus cycle time (read) figure 4. current vers us cycle time (write) table 1. hardware mode selection ce we a12?a0 mode i/o notes l h 0x0000 0x1555 0x0aaa 0x1fff 0x10f0 0x0f0f read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z [1] l h 0x0000 0x1555 0x0aaa 0x1fff 0x10f0 0x0f0e read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z [1] note 1. the six consecutive addresses must be in the order listed. we must be high during all six consecutive ce controlled cycles to enable a nonvolatile cycle.
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 6 of 17 maximum ratings exceeding maximum ratings may s horten the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c temperature under bias. ............ ............... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd ... .....?0.5 v to 7.0 v voltage on input relative to v ss ......... ?0.6 v to v cc + 0.5 v voltage on dq 0-7 ................................ ?0.5 v to v cc + 0.5 v power dissipation ........................................................ 1.0 w dc output current (1 output at a time, 1s duration).... 15 ma operating range range ambient temperature v cc military -55 ? c to +125 ? c 4.5 v to 5.5 v dc electrical characteristics over the operating range (v cc = 4.5 v to 5.5 v) parameter description test conditions min max unit i cc1 average v cc current t rc = 35 ns t rc = 45 ns t rc = 55 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma ?75 65 55 ma ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store ?3ma i cc3 average v cc current at t rc = 200 ns, 5 v, 25 c typical we > (v cc ? 0.2 v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. ?10ma i sb1 [2] v cc standby current (standby, cycling ttl input levels) t rc = 35 ns, ce > v ih t rc = 45 ns, ce > v ih t rc = 55 ns, ce > v ih ?24 21 20 ma ma ma i sb2 [2] v cc standby current ce > (v cc ? 0.2 v). all others v in < 0.2 v or > (v cc ? 0.2 v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz ? 1500 ? a i ix input leakage current v cc = max, v ss < v in < v cc ?1 +1 ? a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il ?5 +5 ? a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?4 ma 2.4 ? v v ol output low voltage i out = 8 ma ? 0.4 v data retention and endurance parameter description min unit data r data retention 100 years nv c nonvolatile store operations 1,000 k capacitance in this table, the capacitance parameters are listed. [3] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 0 to 3.0 v 8pf c out output capacitance 7pf note 2. ce > v ih does not produce standby current levels until any nonvolatile cycle in progress has timed out. 3. these parameters are guaranteed by design and are not tested.
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 7 of 17 thermal resistance in this table, the thermal re sistance parameters are listed. [4] parameter description test conditions 28-cdip 28-lcc unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and proce- dures for measuring thermal impedance, per eia / jesd51. tbd tbd ? c/w ? jc thermal resistance (junction to case) tbd tbd ? c/w figure 5. ac test loads ac test conditions 5.0 v output 30 pf r1 480 ? r2 255 ? input pulse levels .................................................. 0 v to 3 v input rise and fall times (10% to 90%) ...................... < 5 ns input and output timing referenc e levels ......... .......... 1.5 v note 4. these parameters are guaranteed by design and are not tested.
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 8 of 17 figure 7. sram read cycle 2: ce and oe controlled [5] ac switching characteristics sram read cycle parameter description 35 ns 45 ns 55 ns unit min max min max min max cypress parameter alt t ace t elqv chip enable access time ? 35 ? 45 ? 55 ns t rc [5] t avav, t eleh read cycle time 35 ? 45 ? 55 ? ns t aa [6] t avqv address access time ? 35 ? 45 ? 55 ns t doe t glqv output enable to data valid ? 15 ? 20 ? 35 ns t oha [6] t axqx output hold after address change 5 ? 5 ? 5 ? ns t lzce [7] t elqx chip enable to output active 5 ? 5 ? 5 ? ns t hzce [7] t ehqz chip disable to output inactive ? 13 ? 15 ? 25 ns t lzoe [7] t glqx output enable to output active 0 ? 0 ? 0 ? ns t hzoe [7] t ghqz output disable to output inactive ? 13 ? 15 ? 25 ns t pu [8] t elicch chip enable to power active 0 ? 0 ? 0 ? ns t pd [8] t ehiccl chip disable to power standby ? 35 ? 45 ? 55 ns switching waveforms figure 6. sram read cycle 1: address controlled [5, 6] notes 5. we must be high during sram read cycles. 6. i/o state assumes ce and oe < v il and we > v ih ; device is continuously selected. 7. measured 200 mv from steady state output voltage. 8. these parameters are guaranteed by design and are not tested. t rc t aa t oha address dq (data out) data valid address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 9 of 17 figure 9. sram write cycle 2: ce and oe controlled [10, 11] sram write cycle parameter description 35 ns 45 ns 55 ns unit min max min max min max cypress parameter alt t wc t avav write cycle time 35 ? 45 ? 55 ? ns t pwe t wlwh, t wleh write pulse width 25 ? 30 ? 45 ? ns t sce t elwh, t eleh chip enable to end of write 25 ? 30 ? 45 ? ns t sd t dvwh, t dveh data setup to end of write 12 ? 15 ? 30 ? ns t hd t whdx, t ehdx data hold after end of write 0 ? 0 ? 0 ? ns t aw t avwh, t aveh address setup to end of write 25 ? 30 ? 45 ? ns t sa t avwl, t avel address setup to start of write 0 ? 0 ? 0 ? ns t ha t whax, t ehax address hold after end of write 0 ? 0 ? 0 ? ns t hzwe [9,10] t wlqz write enable to output disable ? 13 ? 15 ? 35 ns t lzwe [9] t whqx output active after end of write 5 ? 5 ? 5 ? ns switching waveforms figure 8. sram write cycle 1: we controlled [10, 11] notes 9. measured 200 mv from steady state output voltage. 10. if we is low when ce goes low, the outputs remain in the high impedance state. 11. ce or we must be greater than v ih during address transitions. t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 10 of 17 autostore inhibit or power up recall parameter alt description stk11c68-5 (smd5962-92324) unit min max t hrecall [12] t restore power up recall duration ? 550 ? s t store t hlhz store cycle duration ? 10 ms v switch low voltage trigger level 4.0 4.5 v v reset low voltage reset level ? 3.6 v figure 10. autostore i nhibit/power up recall v cc v switch v reset power-up recall dq (data out) store inhibit 5v t hrecall power-up recall brown out store inhibit no recall (v cc did not go below v reset ) brown out store inhibit no recall (v cc did not go below v reset ) brown out store inhibit recall when v cc returns above v switch nt 12. t hrecall starts from the time v cc rises above v switch .
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 11 of 17 software controlled store/recall cycle the software controlled store/recall cycle follows. [13, 14] parameter alt description 35 ns 45 ns 55 ns unit min max min max min max t rc t avav store/recall initiation cycle time 35 ? 45 ? 55 ? ns t sa [13] t avel address setup time 0 ? 0 ? 0 ? ns t cw [13] t eleh clock pulse width 25 ? 30 ? 35 ? ns t hace [13] t elax address hold time 20 ? 20 ? 20 ? ns t recall [13] recall duration ? 20 ? 20 ? 20 ? s switching waveform figure 11. ce controlled software store/recall cycle [13] notes 13. the software sequence is clocked on the falling edge of ce without involving oe (double clocking aborts the sequence). 14. the six consecutive addresses must be read in the order listed in table 1 on page 5 . we must be high during all six consecutive cycles. t rc t rc t sa t sce t hace t store / t recall data valid data valid 6 # s s e r d d a 1 # s s e r d d a high impedance address ce oe dq (data)
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 12 of 17 speed: 35 - 35 ns 45 - 45 ns package: c = ceramic 28-pin 300 mil dip (gold lead finish) part numbering nomenclature stk11c68 - 5 c 45 m temperature range: m - military (-55 to 125 c) k l = ceramic 28-pin llc = ceramic 28-pin 300 mil dip (solder dip finish) retention / endurance 5 = military (10 years or 10 5 cycles) 55 - 55 ns case outline x = ceramic 28-pin 300 mil dip y = ceramic 28-pin llc device class indicator - class m smd5962-92324 04 mx x lead finish a = solder dip lead finish device type: 04 = 55 ns 05 = 45 ns c = gold lead dip finish x = lead finish ?a? or ?c? is acceptable 06 = 35 ns
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 13 of 17 ordering information speed (ns) ordering code package diagram package type operating range 35 stk11c68-5l35m 001-51696 28-pin lcc (350 mil) military 55 stk11c68-5c55m 001-51695 28-pin cdip (300 mil) stk11c68-5k55m 001-51695 28-pin cdip (300 mil) stk11c68-5l55m 001-51696 28-pin lcc (350 mil) this table contains final information. contact your local cypress sales representative for availability of these parts.
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 14 of 17 package diagrams figure 12. 28-pin (300-mil) side braze dil (001-51695) 001-51695 *a
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 15 of 17 figure 13. 28-pad (350-mil) lcc (001-51696) package diagrams (continued) 001-51696 *a
stk11c68-5 (smd5962-92324) document number: 001-51001 rev. *c page 16 of 17 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output i/o input/output nvsram nonvolatile static random access memory oe output enable sram static random access memory ttl transistor-transistor logic we write enable symbol unit of measure c degrees celsius k ? kilohm ? a microampere ma milliampere ? f microfarad ? s microsecond ms millisecond ns nanosecond pf picofarad v volt ? ohm w watt
document number: 001-51001 rev. *c revised february 16, 2012 page 17 of 17 autostore and quantumtrap are registered trademarks of cypress semiconductor corporation. all products and company names mentio ned in this document may be the trademarks of their respective holders. stk11c68-5 (smd5962-92324) ? cypress semiconductor corporation, 2009-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: stk11c68-5 (smd5962-92324) 64 kbit (8 k x 8) softstore nvsram document number: 001-51001 rev. ecn no. orig. of change submission date description of change ** 2666844 gvch/pyrs 03/02/2009 new data sheet *a 2685053 gvch 04/07/2009 added part numbers: stk11c68-5k45m and stk11c68-5k55m *b 3054310 gvch/keer 10/1120/10 removed inactive parts - stk11c68-5c35m, stk11c68-5k35m, stk11c68-5c45m, stk11c68-5k45m, stk11c68-5l45m from ordering code information table. updated package diagrams. *c 3527665 gvch 02/16/2012 added acronyms, docum ent conventions, and table of contents. completing sunset review.

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